module ro_field #(
    parameter WD   = 32,
    parameter RST  = {WD{1'b0}},
    parameter MODE = 0 //rtl first, cpu next
)(
    input  clk,
    input  rst_n,

    input  rtl_wen,
    input  [WD -1:0]rtl_wdata,

    output [WD -1:0]rdata
);

reg [WD -1:0]field;
always @(posedge clk or negedge rst_n)begin
    if(!rst_n)
        field <= RST;
    else if(rtl_wen)
        field <= rtl_wdata;
end

assign rdata = field;

endmodule
